In general, large devices are used in CMOS buffers to drive large loads at high speeds. These large devices can sink or source large amounts of current and are turned on and off in short time durations. However, parasitic inductances are always present at chip package supply pins and, thus, inductive voltage transients can exceed the noise margin requirements. Further, this problem is exacerbated when many outputs are switching together. As a result, when high speed is required, an acceptable noise margin is typically difficult to obtain without special input/output (I/O) customization. Further, switching noise has become even more of a problem as circuits are required to run at higher frequencies, and as noise sensitive analog circuit functions are integrated with digital circuits.
At least one attempt that prior art has made to solve this problem is to control the drive to the gate of the output devices by, for example, an RC circuit. However, this approach requires the use of resistors and the choice of the values for the resistors cannot be optimized for different loading. Moreover, the RC circuit substantially increases propagation delay.
Another attempt made by prior art is the use of a staggered turn on/turn off of the output devices. However, this approach requires fine tuning of the cascaded turn on/turn off for each of the output devices, and the fine tuning does not take loading effects into account.
Hence, there exists a need for an improved high speed, low noise CMOS driver having optimized speed/noise trade off characteristics.